“Precise Timing for Best Design”
The Company provides new truly statistical timing signoff tools and consulting for complex digital designs (SoC) implemented in deep-submicron 28-to-7nm technologies.
- 20-500x reduction of Timing ECO Design Cycle
- 8%-20% better Timing Accuracy & Excellent Correlation to Hspice
- Delivering Timing Yield requested by the designer w/o unexpected silicon failures
- Removing Optimism & Risk in ~0.5% paths
- Removing Pessimism, Over-designing & Over-margining in ~94% paths
- Using truly Statistical methods of estimating Global & Local Variations from all variation sources
All tools are complementary to current commercial STA tools & design flows. Company has developed new timing signoff paradigms, methodologies & statistical tools that are superior to commercially available STA/SSTA tools. The tools prevent timing violations in critical paths that lead to silicon failure & remove timing pessimism in the rest of paths. Abelite’s unique & Monte Carlo-based statistical tools offer:
- Modeling all conceivable global/local, random/correlated sources of variations including EDA tools/flow/libraries inaccuracies/errors, PVT & geometry variations in cells, wires/vias, Double Patterning Technology (DPT), Aging Degradation (AD), Layout Dependent Effects (LDE) & FinFET
- Estimating timing yield & power consumption
- Achieving timing signoff with needed confidence & with taking into account the number of timing critical paths
- Performing optional signoff at all needed PVT/RC/Via/AD/DPT corners
Abelite methodology prevents silicon failure while improving design performance, power & area, obtaining best QoR & reduces TAT, Costs & TTM. Methodology & tools were verified on multiple test-cases for several technology nodes. Customers are not required to change their EDA tools & design flows. All Abelite tools & methodologies are unique & not available from other EDA vendors.